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Open research questions in Parallel Computing and Optimization Techniques

132 unresolved questions extracted from the limitations and future-work sections of 687 Parallel Computing and Optimization Techniques papers in our library. Each links back to the study that raised it.

What the literature leaves open

  • Building on KVDrive, our future research will focus on three key directions. First, we aim to extend our holistic management to multimodal models, which present distinct KV cache access patterns compared to text-only LLMs. Second, we plan to investigate Processing-in-Memory hardware to offload selection and partial computation directly into storage tiers, further mitigating data movement bottlenecks. Finally, we plan to explore the synergy between KVDrive and compression techniques, such as quantization and pruning. We envision a Tiered Mixed-Precision Storage scheme that leverages KVDrive’s ability to distinguish hot and cold KV blocks and assigns precision adaptively across tiers: maintaining high precision (e.g., FP16) for latency-critical hot blocks in HBM, while applying more aggressive quantization (e.g., INT4) to cold blocks spilled to SSD. This design trades modest (de)quantization overhead for higher effective I/O bandwidth and storage capacity, aiming to alleviate the I/O bottleneck in massive-context retrieval while preserving end-to-end generation quality.

    KVDrive: A Holistic Multi-Tier KV Cache Management System for Long-Context LLM Inference · 2026

  • The complexity of optimizing data layouts for bounding volume hierarchies, which depends on the algorithm, hardware architecture, and characteristics of the input data. The need to balance runtime performance and memory utilization when optimizing data layouts. The challenge of verifying the correctness of the Scion compiler, which requires a combination of static analyses and proof sketches.

    Decoupling Data Layouts from Bounding Volume Hierarchies · 2026 · DOI

  • The entanglement of data layout choices with traversal logic prevents independent optimization of data layouts and algorithms. The lack of a domain-specific language and compiler for specifying data layouts of bounding volume hierarchies independently of tree traversal algorithms. The need for a systematic approach to exploring the design space of data layouts for bounding volume hierarchies.

    Decoupling Data Layouts from Bounding Volume Hierarchies · 2026 · DOI

  • Investigating the application of LSQ to other capacitated vehicle routing problems, - Exploring the use of other quantum-inspired solvers for CVRPTW, - Developing a more efficient dynamic-penalty encoding, - Applying LSQ to larger instances of CVRPTW

    Hardware-Aware Sparse QUBO Encoding for CVRPTW on Coherent Ising Machines: An LKH-Guided Variable-Compression Framework · 2026 · DOI

  • The lack of a scalable method for solving CVRPTW. The limitation of current methods in terms of their ability to handle large problem sizes. The need for a new framework that can efficiently solve CVRPTW.

    Hardware-Aware Sparse QUBO Encoding for CVRPTW on Coherent Ising Machines: An LKH-Guided Variable-Compression Framework · 2026 · DOI

  • To handle the challenges posed by varying sparsity levels across sub-blocks, we introduce a block-wise column aggregation strat- egy that consolidates sparse data and a format-adaptive selection mechanism that chooses suitable storage for each sub-block.

    CB-SpMV:A Data Aggregating and Balance Algorithm for Cache-Friendly Block-Based SpMV on GPUs · 2026

  • GPU high bandwidth memory is scarce and expensive, and KV caches consume much of it as chats, agent loops, and document question answering accumulate state.

    Where Should the KV Cache Live? Placement Policies Across GPU, CPU, and SSD for Long-Lived Sessions · 2026

  • Instrumented binaries run much slower than production builds and have memory efficiency issues. Selective instrumentation and adaptive profiling are needed to balance insight quality and system performance. Privacy concerns are raised when profiling production traffic at scale.

    Closed-Loop Binary Optimization: Integrating De-Identified Production Telemetry into the Build Lifecycle · 2026 · DOI

  • There is a gap between compiling source code to machine code and executing instructions on the processor. Static compilation cannot predict dynamic control flow and cache behavior.

    Closed-Loop Binary Optimization: Integrating De-Identified Production Telemetry into the Build Lifecycle · 2026 · DOI

  • Existing Rust-based data libraries focus primarily on either API breadth or specialized domains. There is a gap for a library that simultaneously provides a comprehensive SIMD-optimized operation stack, first-class bindings for both Python and WebAssembly, custom memory management, and modular feature composition.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Compilation time overhead from Rust monomorphization with full SIMD feature flags is mentioned but not quantified; a systematic analysis comparing incremental vs. full compilation times across feature subsets (CSV-only, CSV + filtering, full feature set) should be conducted to characterize the compile-time vs. runtime performance trade-off in Veloxx's feature flag system.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Memory access bottleneck in multi-core parallelism. Limited registers within a DSP core. Instruction-level parallelism (ILP) optimization.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • Traditional optimizations for CPUs and GPUs are not easily applicable to modern DSPs. There is a need for efficient GEMM libraries that can maximize computational capabilities and bandwidth utilization of multi-core DSPs.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • Existing analysis approaches have significant limitations. There is a need for a memory-centric analysis framework that can provide detailed insights into system behavior.

    An integrated framework for memory-centric analysis: from trace collection to co-design · 2026 · DOI

  • The Memory Wall bottleneck manifests as two primary efficiency taxes: the Transcoding Tax and the Branching Tax. Prior work has not addressed the runtime transposition of live data streams.

    AarchGate: A Domain-General Bit-Sliced JIT Execution Primitive for ARM64 - Technical Architecture and Implementation · 2026 · DOI

  • Future work will explore the integration of SVE2 (Scalable Vector Extensions) for wider logic gates, the expansion of the bit-sliced model to complex join operations and multi-dimensional spatial queries, and the application of this primitive to emerging domains such as real-time feature extraction for large-scale ML pipelines.

    AarchGate: A Domain-General Bit-Sliced JIT Execution Primitive for ARM64 - Technical Architecture and Implementation · 2026 · DOI

  • The current paradigm assumes a static vertical topology, leading to a substantial misallocation of computational resources. Recent developments in horizontal sparsity attempt to mitigate this but introduce severe hardware inefficiencies.

    In-Depth-MoE: Predictive Sequence-Level Gatingvia Speculative Layer Allocation · 2026 · DOI

  • , models with billions of parameters trained on diverse web-scale corpora) remains an open challenge requiring cluster-level hardware testing. However, a key limitation of the current empirical validation must be acknowledged: these experiments were conducted on a scaled-down, toy transformer model utilizing synthetic data distributions.

    In-Depth-MoE: Predictive Sequence-Level Gatingvia Speculative Layer Allocation · 2026 · DOI

  • INT2 KV-cache quantization is a challenging problem for long-context LLM serving. Simple rotations such as Hadamard transforms are not aligned with downstream attention.

    OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization · 2026

  • 3DGS rendering remains too expensive for many latency-sensitive scenarios. Exploiting Tensor Cores for 3DGS is non-trivial because rasterization does not naturally match their execution model.

    Accelerating 3D Gaussian Splatting using Tensor Cores · 2026

  • Prior works have limitations in optimizing MoE inference for throughput-oriented workloads on resource-constrained single-GPU systems. Existing approaches using expert offloading or micro-batching have limitations in reducing GPU memory pressure.

    CoX-MoE: Coalesced Expert Execution for High-Throughput MoE Inference with AMX-Enabled CPU-GPU Co-Execution · 2026

  • The computational cost of exact GP inference. The heavy dependency footprint of existing Python libraries like GPyTorch.

    Lightweight Gaussian Process Inference in C++ on Metal and CUDA · 2026

  • Existing bucket-based data loading strategies fail to account for the quadratic complexity of self-attention mechanisms. Computational synchronization bottlenecks in video diffusion Transformers.

    AdaptiveLoad: Towards Efficient Video Diffusion Transformer Training · 2026

  • The evaluation of the statistical quality of PRNGs is challenging due to the complexity of the tests. The selection of the best PRNG for a specific application is difficult due to the lack of guidance. The development of new PRNGs with improved statistical quality is a challenging task.

    ASSESSING THE STOCHASTIC PROPERTIES OF MODERN PSEUDO-RANDOM GENERATORS FOR PARALLEL COMPUTING · 2026

  • The study only evaluates a limited number of generators. The tests are conducted under consistent conditions, but may not reflect real-world usage. The study does not provide a comprehensive comparison of all available generators.

    ASSESSING THE STOCHASTIC PROPERTIES OF MODERN PSEUDO-RANDOM GENERATORS FOR PARALLEL COMPUTING · 2026

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132 open questions have been extracted from the limitations and future-work passages of 687 Parallel Computing and Optimization Techniques papers in our library. Each one below links back to the study that raised it, so you can read the original claim in context.

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