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Open research questions in Parallel Computing and Optimization Techniques

42 unresolved questions extracted from the limitations and future-work sections of 503 Parallel Computing and Optimization Techniques papers in our library. Each links back to the study that raised it.

What the literature leaves open

  • Based on these findings, further study is necessary to characterize the DMA through- put penalty across a range of payload sizes to localize its mechanism at the peripheral interface level, and to perform register-level analysis of the bus interactions between each core and the shared SHA-256 accelerator.

    Comparative energy awareness and performance analysis of ARM and RISC-V SHA-256 hardware acceleration on the RP2350 · 2026 · DOI

  • Our work demonstrates that the acceleration of detailed timing simulations for MPSoCs on gem5 is achievable through the use of PDES, effectively harnessing the computational power of modern multi-core simulation hosts. In this context, parti- gem5 serves as a valuable addition to existing methods, such as sampling and check- pointing, by enabling rapid exploration of micro-architectures. One notable advantage of our approach is its ability to simulate larger portions of the target software applications with detailed models. The extent of speedup achieved relies on the scalability of the simulated multi-thread software workload. 1 3International Journal of Parallel Programming (2026) 54:16 Page 19 of 22 16 Fig. 10 Error distribution in cache statistics for four quantum settings Fig. 11 Error distribution in DRAM statistics for four quantum settings Our evaluations reveal that applications with limited data sharing greatly benefit from parti-gem5. Using a set of 16 benchmarks on a 32-core target platform, we with a mean of 10.52 showed speedups up to 18.18 Despite the introduction of timing inaccuracies due to the non-determinism of parallel simulations, the deviations in simulated time can be bound to an acceptable range by setting a quantum-based on the latencies of the target system. We showed that for a quantum value just below the hit latency of the non-private cache (4ns in our experiments) leads to an error below 5% for all sixteen benchmarks. With this setting, parti-gem5 can deliver reliable key activity indicators such as power states . × × 1 3International Journal of Parallel Programming… 16 Page 20 of 22 and operation counters for CPU, cache and DRAM modules. The combined MAPE for these metrics is 2.62%. Although we did not encounter any causality errors that affected the correctness of the simulated workloads, conducting more formal verification to validate the cor- rectness and preservation of memory consistency would be an important contribution to our work. While our evaluation was focused on the ARM ISA, the concepts we introduced can be extended to any other target architecture. Further experimentation is neces- sary to explore simulation performance for other interconnect topologies and soft- ware workloads. Nevertheless, we hope our contributions inspire and enable further advancements in this field. New development efforts in simulation infrastructure should consider the perfor- mance benefits of multi-core host platforms early in the design process. This implies creating models and transmission protocols which are thread-safe by design. Author Contributions J.C. wrote the main manuscript text. J.C., N.Z., and J.N. worked on the develop- ment, testing, and benchmarking of the parti-gem5 SW. These three authors prepared all the tables and figures. R.L. is the head of the department and provided ample scientific guidance. J.J. acted as principal investigator and project manager in this project. All authors reviewed the manuscript. Funding Open Access funding enabled and organized by Projekt DEAL. Data Availability No datasets were generated or analysed during the current study.

    Scalable and Accurate Parallel Timing Simulations with parti-gem5 · 2026 · DOI

  • Long-context language model inference is increasingly limited by the memory bandwidth and capacity required to store key-value caches, yet existing compression methods often apply uniform budgets across layers or tokens and degrade retrieval when lexical cues and semantic states require different preservation.

    DepthWeave-KV: Token-Adaptive Cross-Layer Residual Factorization for Long-Context KV Cache Compression · 2026

  • Long-context LLM inference is increasingly limited by the memory and bandwidth cost of KV caches, yet aggressive compression can remove the layer-specific evidence needed for retrieval and multi-step reasoning.

    FreqDepthKV: Frequency-Guided Depth Sharing for Robust KV Cache Compression in Long-Context LLM Inference · 2026

  • We argue the bottleneck is encoding density, not expressiveness, and present LSQ, a hardware-aware sparse Quadratic Unconstrained Binary Optimization (QUBO) framework that decouples CVRPTW into a compact customer-to-route assignment QUBO and a classical intra-route ordering step under a soft no-wait service convention.

    Hardware-Aware Sparse QUBO Encoding for CVRPTW on Coherent Ising Machines: An LKH-Guided Variable-Compression Framework · 2026 · DOI

  • Our implementation, HamSim, utilizes a compact diagonal-sparse data layout and specialized C++/CUDA kernels to bypass the overheads of generic formats like CSR.

    Diagonal-Budgeted Trotterization for Efficient Quantum Hamiltonian Simulation · 2026

  • Agentic AI is promising for producing parallel Julia code, but generating robust, performance-aware implementations for large-scale HPC systems remains an open challenge.

    Generated, Parallel, Scalable? A Study of Agentic AI-Generated Julia Code on Supercomputers · 2026

  • In this work, we first survey the inference landscape, identifying 200 distinct engines, and analyze 35,000 ML publications, finding that the specific inference stack is rarely reported despite this widespread diversity.

    The Silent Hyperparameter: Quantifying the Impact of Inference Backends on LLM Reproducibility · 2026

  • Spike-aware execution can improve CPU throughput and memory behavior for sparse spiking language models, while model quality, controlled dense training baselines, embodied-task evaluation, and measured CPU energy remain open problems.

    Spike-Aware C++ INT8 Inference for Sparse Spiking Language Models on Commodity CPUs · 2026

  • Our method requires JDK 16 or newer due to mapMulti, is hardwired to the Stream API tested on JDK 24, and currently transforms only map and filter among the eleven intermediate operations (dropWhile, flatMap, gather, limit, peek, skip, sorted, takeWhile, etc.). We cannot fuse closures — lambdas capturing outer variables — because bytecode places ILOAD and ALOAD instructions between stream operations, breaking the consecutive pattern our rewriting rules expect. Similarly, we cannot fuse functional objects (e.g., new Square() instead of lambdas) as they compile to new/invokespecial rather than invokedynamic. Code relying on Reflection to inspect bytecode structure may break, though such practice is uncommon. Line metadata may be damaged, affecting debugging.

    Compile-Time Java Stream Fusion via mapMulti · 2026 · DOI

  • , models with billions of parameters trained on diverse web-scale corpora) remains an open challenge requiring cluster-level hardware testing. However, a key limitation of the current empirical validation must be acknowledged: these experiments were conducted on a scaled-down, toy transformer model utilizing synthetic data distributions.

    In-Depth-MoE: Predictive Sequence-Level Gatingvia Speculative Layer Allocation · 2026 · DOI

  • Future work will explore the integration of SVE2 (Scalable Vector Extensions) for wider logic gates, the expansion of the bit-sliced model to complex join operations and multi-dimensional spatial queries, and the application of this primitive to emerging domains such as real-time feature extraction for large-scale ML pipelines.

    AarchGate: A Domain-General Bit-Sliced JIT Execution Primitive for ARM64 - Technical Architecture and Implementation · 2026 · DOI

  • Compilation time overhead from Rust monomorphization with full SIMD feature flags is mentioned but not quantified; a systematic analysis comparing incremental vs. full compilation times across feature subsets (CSV-only, CSV + filtering, full feature set) should be conducted to characterize the compile-time vs. runtime performance trade-off in Veloxx's feature flag system.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • The TPC-H evaluation of Veloxx is limited to a simplified 500K-row workload; full TPC-H benchmark execution (Queries 1–22) with standard scale factors (1GB, 10GB, 100GB) must be performed to validate whether SIMD-accelerated columnar operations and custom memory pooling maintain competitive advantage at realistic analytical workload complexity and scale.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Parallel scaling of group-by operations achieves only 51% parallel efficiency at 16 threads due to merge-phase synchronization overhead with the empirically-tuned 8,192-element chunk size; investigation of adaptive chunking strategies, lock-free merge algorithms, and scaling beyond 16 threads is needed to reduce synchronization bottlenecks in Veloxx's parallelism.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Benchmarking of Veloxx's SIMD-accelerated operations relied on synthetic 100K–10M element datasets; validation against real-world datasets exhibiting data skew, heterogeneous column types, and sparse null distributions is required to determine whether the observed 2.7–5.6× and 25.9× improvements hold under production-realistic conditions.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Group-by aggregation in Veloxx supports only sum, mean, min, max, and count; quantile, distinct count, and first/last aggregations must be implemented with SIMD-optimized hash + parallel merging strategies to assess whether the 25.9× group-by throughput improvement generalizes to these advanced analytical operations.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Veloxx's join operation currently supports only single-key joins with SimdHashTable; multi-key joins, asof joins, and cross joins must be implemented and benchmarked against Polars to determine whether SIMD acceleration strategies can maintain the observed 2–12× throughput advantage across these join variants.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • The validity bitmap implementation using Vec<bool> introduces ~20% overhead in Veloxx's columnar operations; a packed bitset representation using Vec<u64> with bit manipulation should be empirically evaluated to quantify overhead reduction and determine whether the memory savings justify implementation complexity for nullable SIMD-accelerated columns.

    Veloxx: An Ultra-High Performance Data Processing Library with SIMD-Accelerated Columnar Operations · 2026 · DOI

  • Performance comparison is limited to MTGEMM variants (with/without fusion) on the same hardware; direct benchmarking against state-of-the-art GEMM libraries optimized for competing multi-core DSP platforms (e.g., TI C66x variants, different cache line sizes) to establish relative efficiency is absent.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • The analytical model in Section V-D determines KA=512 as optimal, but this derivation assumes specific DDR bandwidth and L1/L2 cache configurations; validation of the model's applicability to other multi-core DSP architectures with different memory hierarchies and peak bandwidth is not addressed.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • The fusion of transpose-add kernels with GEMM computation demonstrates 8.9-47.0% improvement depending on KA, but the paper does not investigate fusion strategies for other common BLAS-2/3 operations (TRSM, SYMM, HEMM) that could exhibit similar vector-reduction overhead on multi-core DSPs.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • While the paper evaluates MTGEMM on fixed matrix dimensions (M=2304, K=2048, NG=1536), performance behavior for highly rectangular matrices (e.g., very large N with small M, or vice versa) and their impact on the proposed data prefetching and operator fusion strategy has not been explored.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • The paper demonstrates that increasing tiling parameter KA (512, 1024, 2048) reduces NA and MS, leading to insufficient micro-kernel overlap and poor multi-core performance; systematic characterization of the optimal KA selection strategy across different matrix sizes and core counts for GEMM on multi-core DSPs is lacking.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

  • The micro-kernel fusion strategy in transpose-GEMM improves single-core performance but degrades multi-core scalability due to increased DDR bandwidth contention; investigation is needed into alternative fusion approaches or bandwidth-aware scheduling mechanisms that can maintain computational efficiency gains while preserving linear speedup across 8+ DSP cores.

    mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs · 2026 · DOI

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42 open questions have been extracted from the limitations and future-work passages of 503 Parallel Computing and Optimization Techniques papers in our library. Each one below links back to the study that raised it, so you can read the original claim in context.

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